4 Bit Parallel Adder

1. OBJECTIVE

Design Tar stay put/objective/calculation
1. To design a lap which pass on have the following criteria:
a. stripped chip area
b. Minimum transistor count
c. Minimum power dissipation
d. Minimum propagation hamper (maximum speed possible)
2. To vex the hand-analyze of the chosen circuit architecture to get maximum performance
3. To prepare the input test vectors and the expected results
4. To produce the testing methodology
5. To prove the circuit is functional and meet every design specification
6. To extract the simulation results.
7. To analyze the differences among the results for hand-analysis, schematic delight and layout

2. BRIEF FUNCTIONAL EXPLANATION

The project performed by this team go forth be the 4 bit parallel common viper. The first tincture in creating this is to focus in designing a 1 bit common viper first. Given below is a configuration of a 1 bit adder. The first stage of the adder is a XNOR gate that has an output voltage of VDD VTN where A and B are both VDD inputs. A full voltage sail XOR gate signal is generated using an inverter. This XOR gate and Cin input signals depart cooperate to generate Cout and SUM outputs with a maximum of iodin VT loss.





Figure 1: 1-bit adder CMOS circuit
This one bit adder after being designed in mentor artistic creation will be confined into a simple emblem below. This symbol will be repeated four times. The Cout will be carried forward until the 4th adder. The symbol is shown below.

Figure 2: !-bit adder symbol
Figure 2: 1-bit adder CMOS symbol
The fn-out are detached from the fan-in using buffer circuits at the inputs and the outputs. They will also help to smoothen the output voltages and reduce the propagation delay of the overall adder.

3. DESIGN METHODOLOGY AND FLOW

Specification / Definition
Schematic Entry
Simulation
Pass?
stimulus Stimulus
Layout
DRC/LVS
Parasitic Extraction
Post-layout Simulation
Tape-out
Input Stimulus
Pass?
No
No
Yes
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